Design-Reuse

IP Verification : Verifying timing of external IP key to SoC success

External intellectual property spans a broad range of technology. It can be as complex as an embedded digital signal processing (DSP) core or as primitive as a RAM instance. IP can come from an ...
Design-Reuse

IP Verification : RTL prototyping: a hardware/software co-verification solution

Traditional ASIC and IP verification methods cannot adequately exercise the hardware and software components of today's designs. This is due to tool performance limitations, which impose a bottleneck ...
EDN

Top ten attributes of successful RTL hand-off

Current ASIC design methodology traditionally is divided into two stages: front-end logical design and back-end physical implementation. The front-end typically includes the design capture, several ...
Electronics Weekly

In FPGA design timing is everything, says Synopsys

When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimising the design to meet ...