Semiconductor Engineering

UVM: It’s Organized And Systematic

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to ...
Design-Reuse

Improving SystemVerilog UVM Transaction Recording and Modeling

This paper will summarize previous work about SystemVerilog [1] UVM [2] transaction recording, transaction modeling and the supporting transaction recording APIs. This discussion will span a wide ...
Semiconductor Engineering

Inside UVM, Take Three

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking ...
Design-Reuse

Power of UVM's Command Line Argument Usage in Verification Test benches

The growing complexity of ASIC/FPGA designs in recent era has caused simulation times to increase drastically. This is because there is a growing need to ensure that the simulation matches the ...