Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous ...

The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire ...

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...

This blog talks about challenges and solutions while reusing the required functional coverage of IP at the SoC level, coverage merging issues, exclusion/removal of groups from functional coverage ...